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1 3a, rad hard, positive, ultra low dropout regulator isl75051srh the isl75051srh is a radiation hardened low-voltage, high-current, single-output ldo specified for up to 3.0a of continuous output current. thes e devices operate over an input voltage range of 2.2v to 6.0v and are capable of providing output voltages of 0.8v to 5.0v adjustable based on resistor divider setting. dropout voltages as low as 65mv can be realized using the device. the ocp pin allows the short circuit output current limit threshold to be programmed by means of a resistor from the ocp pin to gnd. the ocp setting range is from 0.5a minimum to 8.5a maximum. the resistor sets the constant current threshold for the output under fault conditions. the thermal shutdown disables the output if the device temperature exceeds the specified value. it subsequently enters an on/off cycle until the fault is removed. the enable feature allows the part to be placed into a low current shutdown mode that typically draws about 1 a. when enabled, the device operates with a typical low ground current of 11ma, which provides for operation with low quiescent power consumption. the device is optimized for fast transient response and single event effects. this reduces the magnitude of set seen on the output. additional protection di odes and filters are not needed. the device is stable with tantal um capacitors as low as 47f and provides excellent regulation all the way from no load to full load. programmable soft-sta rt allows the user to program the inrush current by means of the decoupling capacitor value used on the byp pin. applications ? ldo regulator for space application ? dsp, fpga and p core power supplies ? post-regulation of swit ched mode power supplies ? down-hole drilling features ? dla smd#5962-11212 ? output current up to 3.0a at t j = 150c ? output accuracy 1.5% over mil temp range ? ultra low dropout: - 65mv typ dropout at 1.0a - 225mv typ dropout at 3.0a ? noise of 100v rms from 300hz to 300khz ? set mitigation with no added filtering/diodes ? input supply range: 2.2v to 6.0v ? fast load transient response ? shutdown current of 1a typ ? output adjustable using external resistors ? psrr 66db typ @ 1khz ? enable and pgood feature ? programmable soft-start/inrush current limiting ? adjustable overcurrent limit from 0.5a to 8.5a ? over-temperature shutdown ? stable with 47f min tantalum capacitor ? 18 ld ceramic flatpack package ? radiation environment - high dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(si) - set/sel/seb . . . . . . . . . . . . . . . . . . . . . . . .86 mev ? cm 2 /mg figure 1. typical application figure 2. dropout vs i out en pg vin ocp rocp 220uf 0.1uf pg vin isl75051srh byp adj vout gnd 0.1uf 220uf 0.1uf r1 r2 2.67k 4.7n 100pf vout vin en 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 i out (a) dropout voltage (v) +125c +25c +150c caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. november 4, 2011 fn7610.1
isl75051srh 2 fn7610.1 november 4, 2011 block diagram reference bias level shift current limit thermal shutdown delay gnd pgood adj vout enable vin power pmos 520mv 450mv bypass ocp current limit adj vadj typical applications en pg vin ocp isl75051srh byp adj vout gnd pg 220uf 0.1uf vin 2.26k 0.1uf 220uf 0.2uf 4.32k 2.67k 4.7n 100pf vout vout vout vout vout vout vin vin vin vin vin en 511 1 9 10 18 2 3 4 5 6 7 8 11 12 13 14 15 16 17 vin 5.49k
isl75051srh 3 fn7610.1 november 4, 2011 pin configuration isl75051srh (18ld cdfp) top view 2 3 4 5 6 7 8 118 17 16 15 14 13 12 11 gnd vout vout vout vout vout vout vadj 910 byp pg vin vin vin vin vin vin ocp en gnd pin descriptions pin number pin name description 12, 13, 14 15, 16, 17 v in input supply pins 18 pg v out in regulation signal. logic low defines when v out is not in regulation. must be grounded if not used. 1gndgnd pin 2, 3, 4 5, 6, 7 v out output voltage pins 8vadjvadj pin allows v out to be programmed with an external resistor divider. 9 byp to filter the internal reference, connect a 0.1f capacitor from byp pin to gnd. 10 en v in independent chip enable. ttl and cmos compatible. 11 ocp allows current limit to be programmed with an external resistor. top lid gnd the top lid is connected to gnd pin of the package.
isl75051srh 4 fn7610.1 november 4, 2011 ordering information ordering number part number (notes 1, 2) temp range (c) package pkg dwg. # 5962r1121201vxc isl75051srhvf -55 to +125 18 ld cdfp k18.d 5962r1121201qxc isl75051srhqf -55 to +125 18 ld cdfp k18.d 5962r1121201v9a isl75051srhvx -55 to +125 die isl75051srhx/sample isl75051srhx/sample -55 to +125 die sample isl75051srhf/proto isl75051srhf/proto -55 to +125 18 ld cdfp k18.d isl75051srheval1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for isl75051srh . for more information on msl please see tech brief tb363 .
isl75051srh 5 fn7610.1 november 4, 2011 absolute maximum rating s thermal information v in relative to gnd (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.7v v out relative to gnd (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.7v pg, en, ocp/adj relative to gnd (note 3). . . . . . . . . . . . . -0.3 to +6.7vdc junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c recommended operating conditions (note 4) ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-55c to +125c junction temperature (t j ) (note 3). . . . . . . . . . . . . . . . . . . . . . . . . . .+150c v in relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2v to 6.0v v out range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8v to 5.0v pg, en, ocp/adj relative to gnd . . . . . . . . . . . . . . . . . . . . . . . 0v to +6.0v thermal resistance (typical) ja (c/w) jc (c/w) 18 ld cdfp package (notes 5, 6) . . . . . . . 28 4 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c radiation information max total dose (dose rate = 50 - 300radsi/s . . . . . . . . . . . . . . . . . . . . . . . 100 krad (si) set (v out < 5% during events (note 7). . . . . . . . . . . . . . 86mev ? cm 2 /mg sel/b (no latchup/burnout . . . . . . . . . . . . . . . . . . . . . . . . 86mev ? cm 2 /mg the output capacitance used for see testing is 220f for c in and c out , 200nf for bypass caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. extended operation at these conditions may compromise reliabi lity. exceeding these limits will result in damage. recommended operating conditions define limits where specifications are guaranteed. 4. refer to ?thermal guidelines? on page 12. 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 6. for jc , the ?case temp? location is the center of the package underside. 7. the device can work down to v out = 0.8v; however, the set performance of < 5% at let = 86mev.cm 2 /mg is guaranteed at v out = >1.5v only. set tests performed with 220f 10v 25m ? and 0.1f cdr04 capacitor on the input and output. electrical specifications unless otherwise noted, all parameters are guaran teed over the followin g specified conditions: v in =v out + 0.4v, v out = 1.8v, c in = c out = 220f 25m ? and 0.1f x7r, t j = +25c, i l = 0a. applications must follow thermal guidelines of the package to determine worst-case junction temperature. please refer to ?applications informat ion? on page 11 of the datasheet and tech brief tb379 . boldface limits apply over the operating temperature range, -55c to +125c. pulse load techniques used by ate to ensure t j = t a defines guaranteed limits. parameter symbol test conditions min (note 8) typ max (note 8) units dc characteristics dc output voltage accuracy v out v out resistor adjust to 0.52v, 1.5v and 1.8v 2.2v < v in < 3.6v; 0a < i load < 3.0a -1.5 0.2 1.5 % v out resistor adjust to 5.0v v out + 0.4v < v in < 6.0v; 0a < i load < 3.0a -1.5 0.2 1.5 % feedback pin v adj 2.2v < v in < 6.0v; i load = 0a 514.8 520 525.2 mv byp pin v byp 2.2v < v in < 6.0v; i load = 0a 520 mv dc input line regulation 2.2v < v in < 3.6v, v out = 1.5v, +25c & -55c (note 9) 1.13 3.5 mv dc input line regulation 2.2v < v in < 3.6v, v out = 1.5v, +125c (note 9) 1.13 8.0 mv dc input line regulation 2.2v < v in < 3.6v, v out = 1.8v, +25c & -55c (note 9) 1.62 3.5 mv dc input line regulation 2.2v < v in < 3.6v, v out = 1.8v, +125c (note 9) 1.62 10.5 mv dc input line regulation v out + 0.4v < v in < 6.0v, v out = 5.0v (note 9) 12.50 20.0 mv dc output load regulation v out = 1.5v; 0a < i load < 3.0a, v in = v out + 0.4v (note 9) -4.0 -0.8 -0.1 mv dc output load regulation v out = 1.8v; 0a < i load < 3.0a, v in = v out + 0.4v (note 9) -4.0 -1.2 -0.05 mv dc output load regulation v out = 5.0v; 0a < i load < 3.0a, v in = v out + 0.4v (note 9) -15.0 -6.0 -0.05 mv
isl75051srh 6 fn7610.1 november 4, 2011 feedback input current v adj = 0.5v 1 a ground pin current i q v out = 1.5v; i load = 0a, v in = 2.2v 11 12 ma ground pin current i q v out = 5.0v; i load = 0a, v in = 6.0v 16 18 ma ground pin current i q v out = 1.5v; i load = 3.0a, v in = 2.2v 11 13 ma ground pin current i q v out = 5.0v; i load = 3.0a, v in = 6.0v 16 18 ma ground pin current in shutdown i shdn enable pin = 0v, v in = 6.0v 1 10 a dropout voltage v do i load = 1.0a, v out = 2.5v (note 10) 65 100 mv dropout voltage v do i load = 2.0a, v out = 2.5v (note 10) 140 200 mv dropout voltage v do i load = 3.0a, v out = 2.5v (note 10) 225 300 mv output short circuit current iscl v out = 0v, v in = 2.2v, r set = 5.11k 1.1 a output short circuit current iscl v out = 0v, v in = 6.0v, r set = 5.11k 1.2 a output short circuit current isch v out = 0v, v in = 2.2v, r set = 511 ? 5.7 a output short circuit current isch v out = 0v, v in = 6.0v, r set = 511 ? 6.2 a thermal shutdown temperature tsd v out + 0.4v < v in < 6.0v 175 c thermal shutdown hysteresis (rising threshold) tsdn v out + 0.4v < v in < 6.0v 25 c ac characteristics input supply ripple rejection psrr v p-p = 300mv, f = 1khz, i load = 3a; v in =2.5v, v out = 1.8v 42 66 db input supply ripple rejection psrr v p-p = 300mv, f = 100khz, i load = 3a; v in = 2.5v, v out = 1.8v 30 db phase margin pm v out =1.8v, c l = 220f tantalum 70 db gain margin gm v out =1.8v, c l = 220f tantalum 16 db output noise voltage i load = 10ma, bw = 300hz < f < 300khz, bypass to gnd capacitor = 0.2f 100 v rms device start-up characteristics: enable pin rising threshold 2.2v < v in < 6.0v 0.6 0.9 1.2 v falling threshold 2.2v < v in < 6.0v 0.47 0.7 0.9 v enable pin leakage current v in = 6.0v, en = 6.0v 1 a enable pin propagation delay v in = 2.2v, en rise to i out rise 225 300 450 s enable pin turn-on delay v in = 2.2v, v out = 1.8v, i load = 1a, c out = 220f, c byp = 0.2f 6ms enable pin turn-on delay v in = 2.2v, v out =1.8v, i load = 1a, c out = 47f, c byp = 0.2f 50 s hysteresis must be independent of v in ; 2.2v < v in < 6.0v 90 200 318 mv device start-up characteristics: pg pin v out error flag rising thre shold 2.2v < vin < 6.0v 85 90 96 % v out error flag falling th reshold 2.2v < vin < 6.0v 82 88 93 % v out error flag hysteresis 2.2v < vin < 6.0v 2.5 3.2 4.0 %v out electrical specifications unless otherwise noted, all parameters are guaran teed over the followin g specified conditions: v in =v out + 0.4v, v out = 1.8v, c in = c out = 220f 25m ? and 0.1f x7r, t j = +25c, i l = 0a. applications must follow thermal guidelines of the package to determine worst-case junction temperature. please refer to ?applications informat ion? on page 11 of the datasheet and tech brief tb379 . boldface limits apply over the operating temperature range, -55c to +125c. pulse load techniques used by ate to ensure t j = t a defines guaranteed limits. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl75051srh 7 fn7610.1 november 4, 2011 error flag low voltage i sink = 1ma 35 100 mv error flag low voltage i sink = 6ma 185 400 mv error flag leakage current v in = 6.0v, pg = 6.0v 0.01 1 a notes: 8. parameters with min and/or max limits are 100% tested at - 55c, +25c and +125c, unless otherwise specified. temperature lim its established by characterization and are not production tested. 9. line and load regulation done under pulsed condition for t<10ms. 10. dropout is defined as the difference between the supply v in and v out, when the supply produces a 2% drop in v out from its nominal value. data measured within a 3ms period. electrical specifications unless otherwise noted, all parameters are guaran teed over the followin g specified conditions: v in =v out + 0.4v, v out = 1.8v, c in = c out = 220f 25m ? and 0.1f x7r, t j = +25c, i l = 0a. applications must follow thermal guidelines of the package to determine worst-case junction temperature. please refer to ?applications informat ion? on page 11 of the datasheet and tech brief tb379 . boldface limits apply over the operating temperature range, -55c to +125c. pulse load techniques used by ate to ensure t j = t a defines guaranteed limits. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units typical operating performance figure 3. load regulation, v out vs i out figure 4. load regulation, v adj vs i out figure 5. load regulation, v out vs i out figure 6. load regulation, v adj vs i out 1.510 1.512 1.514 1.516 1.518 1.520 1.522 1.524 1.526 1.528 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i out (a) v out (v) +25c, v out (mv) -58c, v out (mv) +128c, v out (mv) v in = 2.5v v out = 1.5v 0.515 0.516 0.517 0.518 0.519 0.520 0.521 0.522 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i out (a) v adj (v) +25c, v adj (mv) -58c, v adj (mv) +128c, v adj (mv) v in = 2.5v v out = 1.5v 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 2.525 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i out (a) v out (v) v in = 3.3v v out = 2.5v +25c, v out (mv) -58c, v out (mv) +128c, v out (mv) 0.5160 0.5165 0.5170 0.5175 0.5180 0.5185 0.5190 0.5195 0.5200 0.5205 0.5210 0.5215 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i out (a) +25c, v adj (mv) -58c, v adj (mv) +128c, v adj (mv) v adj (v) v in = 3.3v v out = 2.5v
isl75051srh 8 fn7610.1 november 4, 2011 figure 7. load regulation, v out vs i out figure 8. load regulation, v adj vs i out figure 9. v in vs v adj over temperature figure 10. r ocp vs ocp at +25c, v out = 1.5v figure 11. r ocp vs ocp at +128c, v out = 1.5v figure 12. r ocp vs ocp at -58c, v out = 1.5v typical operating performance (continued) 4.060 4.065 4.070 4.075 4.080 4.085 4.090 0.00.51.01.52.02.53.03.5 i out (a) v out (v) v in = 5v v out = 4v +25c, v out (mv) -58c, v out (mv) +128c, v out (mv) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i out (a) v in = 5v v out = 4v +25c, v adj (mv) -58c, v adj (mv) +128c, v adj (mv) v adj (v) 0.5160 0.5165 0.5170 0.5175 0.5180 0.5185 0.5190 0.5195 0.5200 0.5205 0.5210 0.5215 0.515 0.517 0.519 0.521 0.523 0.525 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 v in (v) v adj (v) +25c, v adj (mv) -58c, v adj (mv) +128c, v adj (mv) 0 1 2 3 4 5 6 7 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 ocp (a) v in (v) r ocp = 1.00k r ocp = 0.75k r ocp = 0.681k r ocp = 0.511k r ocp = 1.47k r ocp = 2.00k r ocp = 3.83 r ocp = 2.61k r ocp = 5.11k 0 1 2 3 4 5 6 7 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 ocp (a) v in (v) r ocp = 0.75k r ocp = 0.681k r ocp = 0.511k r ocp = 1.47k r ocp = 2.61k r ocp = 1.00k r ocp = 2.00k r ocp = 3.83 r ocp = 5.11k 0 1 2 3 4 5 6 7 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 ocp (a) v in (v) r ocp = 0.75k r ocp = 0.681k r ocp = 0.511k r ocp = 1.47k r ocp = 2.61k r ocp = 1.00k r ocp = 2.00k r ocp = 3.83 r ocp = 5.11k
isl75051srh 9 fn7610.1 november 4, 2011 figure 13. transient load response, v in = 3.3v, v out =2.5v, c out = 47f, 35m ? figure 14. transient load response, v in = 3.3v, v out =2.5v, c out = 220f, 25m ? figure 15. power-on and power-off, en = 0 to 1, +25c, v in = 6v, v out = 0.8v, i out = 0.5a, pgood turn-on figure 16. power-on and power-off, en = 0 to 1, +25c, v in = 2.2v, v out = 0.8v, i out = 0.5a, pgood turn-on figure 17. power-on and power-off, en = 1 to 0, +25c, v in = 6v, v out = 0.8v, i out = 0.5a, pgood turn-off figure 18. power-on and power-off, en = 1 to 0, +25c, v in = 2.2v, v out = 0.8v, i out = 0.5a, pgood turn-off typical operating performance (continued)
isl75051srh 10 fn7610.1 november 4, 2011 figure 19. noise (v/ hz o.5) figure 20. psrr typical operating performance (continued) 0 20 40 60 80 100 120 140 0 50k 100k 150k 200k 250k 300k frequency (hz) noise (v/ hz 0.5) > > >
isl75051srh 11 fn7610.1 november 4, 2011 applications information input voltage requirements this rh ldo will work from a v in in the range of 2.2v to 6.0v. the input supply can have a tolerance of as much as 10% for conditions noted in the ?electrical specifications? table starting on page 5. minimum guaranteed input voltage is 2.2v. however, due to the nature of an ldo, v in must be some margin higher than the output voltage, plus dropout at the maximum rated current of the application, if acti ve filtering (psrr) is expected from v in to v out . the dropout spec of this family of ldos has been generously specified to allow applications to design for efficient operation. adjustable output voltage the output voltage of the rh ldo can be set to any user programmable level between 0.8v to 5.0v. this is achieved with a resistor divider connected between the out, adj and gnd pins. with the internal reference at 0.52v, the divider ratio should be fixed such that when the desired vout level is reached, the voltage presented to the adj pin is 0.52v. resistor values for typical voltages are shown in table 1. input and output capacitor selection rh operation requires the use of a combination of tantalum and ceramic capacitors to achieve a good volume-to-capacitance ratio. the recommended combination is a 220f, 25m ? 10v dssc 04051-032 rated tantalum ca pacitor in parallel with a 0.1f mil-prf-49470 cdr04 ceramic capacitor, to be connected between v in to gnd pins and v out to gnd pins of the ldo, with pcb traces no longer than 0.5cm. the stability of the device depends on the capacitance and esr of the output capacitor. the usable esr range for the device is 6m ? to 100m ? . at the lower limit of esr = 6m ? , the phase margin is about 51c. on the high side, an esr of 100m ? is found to limit the gain margin at around 10db. the typical gm/pm seen with capacitors are shown in table 2. type numbers of kemet capacitors used in the device are shown in table 3. a typical gain phase plot measured on the isl75051srheval1z evaluation board for v in = 3.3v, v out = 1.8v and i out = 3a with a 220f, 10v, 25m ? capacitor is shown in figure 21 and is measured at gm = 16.3db and pm = 69.16. enable the device can be enabled by applying a logic high on the en pin. the enable threshold is typically 0.9v. a soft-start cycle is initiated when the device is enabled using this pin. taking this pin to logic low disables the device. en can be driven from either an open drain or a totem pole logic drive between en pin and gnd. assuming an open drain configuration, m1 will actively pull down the en line, as shown in figure 22, and thereby discharge the input capacitance, shutting off the device immediately. table 1. resistor values for typical voltages v out r top r bottom 0.8v 7.87k 4.32k 1.5v 2.26k 4.32k 1.8v 1.74k 4.32k 2.5v 1.13k 4.32k 4.0v 634 4.32k 5.0v 499 4.32k table 2. typical gm/pm with various capacitors capacitance (f) esr (m ? ) gain margin (db) phase margin () 47 35 14 55 100 25 16 57 220 6 19 51 220 25 16 69 100 100 10 62 table 3. kemet capacitors used in device kemet type number capacitor details t525d476m016ate035 47f, 10v, 35m ? t525d107m010ate025 100f, 10v, 25m ? t530d227m010ate006 220f, 10v, 6m ? t525d227m010ate025 220f, 10v, 25m ? t495x107k016ate100 100f, 16v, 100m ? figure 21. typical gain phase plot -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 500 5k 50k 500k 5m phase () gain (db) frequency (hz) 3.3v 1.8v 3.0a t525d 1x220f gain phase
isl75051srh 12 fn7610.1 november 4, 2011 power good the power-good pin is asserted high when the voltage on the adj pin crosses the rising threshold of 0.9 x v adj typ. on the falling threshold, power-good is asserted low when the voltage on the adj pin crosses the falling threshold of 0.88 x v adj . the power-good output is an open-drain output rated for a continuous sink current of 1ma. soft-start soft-start is achieved by means of the charging time constant of the byp pin. the capacitor value on the pin determines the time constant and can be calculated using equation 1: where t s = soft-start time in ms, and c s = bypass capacitor in nf. the bypass capacitor, c1, charges with a 90a source current and provides an ea reference, -in, with an ss ramp. v out , in turn, follows this ramp. the ramp rate can be calculated based on the c1 value. for conditions in which c1 is opened, or for small values of c1, the ramp is provided by c2 = 50pf, with a source of 0.5a. connecting c1 min = 0.1f to the bypass pin is recommended for normal operation. current limit protection the rh ldo incorporates protection against overcurrent due to any short or overload condition applied to the output pin. the current limit circuit becomes a co nstant current source when the output current exceeds the current limit threshold, which can be adjusted by means of a resistor connected between the ocp pin and gnd. if the short or overload condition is removed from v out , then the output returns to norm al voltage mode regulation. ocp can be calculated with equation 2: where ocp = overcurrent threshold in amps, and rocp = ocp resistor in k ? . in the event of an overload condition based on the set ocp limit, the die temperature may exceed the internal over-temperature limit, and the ldo begins to cycle on and off due to the fault condition (figure 24). however, thermal cycling may never occur if the heatsink used for the package can keep the die temperature below the limits specified for thermal shutdown. thermal guidelines if the die temperature exceeds typically +175c, then the ldo output shuts down to zero until the die temperature cools to typically +155c. the level of po wer combined wi th the thermal impedance of the package ( jc of 4c/w for the 18 ld cdfp package) determines whether the junction temperature exceeds the thermal shutdown temperatur e specified in the ?electrical specifications? table. the device should be mounted on a high effective thermal conductivity pcb with thermal vias, per jesd51-7 and jesd51-5. place a silpad between package base and pcb copper plane. the vin and vout ratios should be sele cted to ensure that dissipation for the selected vin range keeps t j within the recommended operating level of 150c for normal operation. int en gate r1 10k m1 int en bus en 0 vin en pin figure 22. enable (eq. 1) t s 0.00577xc s = u1 isl75051srh ea +in -in -in out i1 90adc i2 0.5adc c1 0.1f c2 50pf adj pin vin vin 0 0 int ss node m1 75051_pmos vin vout bypass ext pin figure 23. soft-start (eq. 2) ocp 9.5 exp 0.6 rocp 1 0.1rocp + () ? () ? ? () ? = 0 1 2 3 4 5 6 7 8 0123456 ocp (a) rocp (k ? ) figure 24. ocp vs rocp over temp ocp = +25c
isl75051srh 13 fn7610.1 november 4, 2011 weight characteristics weight of packaged device k18.d: 1.07 grams typical with leads clipped die characteristics die dimensions 4555m x 4555m (179.3 mils x 179.3 mils) thickness: 304.8m 25.4m (12.0 mils 1 mil) interface materials glassivation type: silicon oxide and silicon nitride thickness: 0.3m 0.03m to 1.2m 0.12m top metallization type: alcu (99.5%/0.5%) thickness: 2.7m 0.4m backside metallization none substrate type: silicon backside finish silicon process 0.6m bicmos junction isolated assembly related information substrate potential unbiased additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 2932 layout characteristics step and repeat 4555m x 4555m metallization mask layout pad name x ? m y ? m 1gnd 0 0 2gnd-3930 3vout-711-710 4 vout -711 -1858 5 vout -711 -2964 6 adj -1680 -3070 7 byp -1621 -3879 8 en 2164 -3879 9 ocp 2222 -3131 10 vin 1078 -2965 11 vin 1078 -1853 12 vin 1078 -711 13 pg 420 -25 pad ? x ? y ? coordinates
isl75051srh 14 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7610.1 november 4, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl75051srh to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change november 4, 2011 fn7610.1 removed ?coming soon? from isl75051srhvf, isl75051srhqf, isl75051srhvx and isl75051srhx/sample in ?ordering information? table on page 4. september 30, 2011 fn7610.0 initial release
isl75051srh 15 fn7610.1 november 4, 2011 package outline drawing k18.d 18 lead ceramic metal seal flatpack package rev 2, 3/11 side view top view section a-a -d- -c- seating and base plane -h- base metal 0.020 (0.508) 0.013 (0.330) 0.040 (1.016 bsc) 0.005 (0.127) min 0.122 (3.10) 0.100 (2.54) 0.397 (10.084) 0.377 (9.576) 0.010 (0.25) 0.004 (0.10) 0.350 (8.89) 0.250 (6.35) 0.03 (0.76) min 0.283 (7.19) min 0.007 (0.178) 0.004 (0.102) 0.010 (0.254) 0.004 (0.102) 0.017 (0.432) 0.013 (0.330) 0.0015 (0.04) max 0.020 (0.508) 0.013 (0.330) 0.015 (0.381) 0.005 (0.127) pin no. 1 id optional 1 2 4 6 3 lead finish 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. 8. notes: dimensioning and tolerancing per ansi y14.5m - 1982. dimensions = inch (mm). c ontrolling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the pin no. 1 id area 0.476 (12.09) 0.456 (11.58) 0.038 (0.97) 0.026 (0.66)

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